Still wondering why it all works? Why this black square does things? Lets go deeper.
Previously I explained a bit about processor architecture. It’s the basis of the chip. It’s a fundament. You won’t find anything about an UART in a Technical Reference Manual of Cortex-M4. It’s just not a part of this fundament.
When you get an STM32 microcontroller based on the Cortex-M4 architecture you just get microcontroller made by ST which uses this specific architecture. What stops them to add to it? Nothing. That’s why you can find so many different models of families and models of processors. Just look at ST’s F and ST’s L series. They are both ARM Cortex-M but they do differ in many ways.
Lets look at what are those from the perspective of someone who programs microcontrollers.
As long as you just need to crunch down some numbers the basic structure of the microcontroller is enough - that’s the ARM architecture. Without external interface you don’t have any input or output. Without any input periphery even programming the controller is impossible, because how would you transfer your instructions into its memory?
In order to learn more lets open STM32F303x6/x8 microcontroller datasheet.
On page 13 you can read a short description:
The Arm 32-bit Cortex -M4 RISC processor with FPU features exceptional co de-efficiency, delivering the high performance expected from an Arm core, with memory sizes usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions that allows efficient signal processing and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.
At the same page you can find summary of the memories types and its sizes. To see exactly how the memory is organized head to page 42. I have attached the image of this page below.
This schematic shows the whole memory layout. Grey cells represent reserved memory - meaning, not for the user. Starting from the address 0x00000000 you can see the part of the memory called CODE. It’s broken down into smaller chunks but among them you will find Flash memory. It starts at 0x080000000 and ends at 0x08010000. That would give a flash memory of 0x00010000, in dec 65536 which equals to 64KB (K = 1024).
Next up is SRAM memory. According to the datasheet this one is 12KB. I will get into more detail in the future but this part of the memory is used during runtime. When the processor is powered off, code and data resides in flash memory, but when you start the processor small code written in Assembler sets everything up by copying data from FLASH to SRAM (it also does other stuff like setting up the stack pointer address but we will get into it later).
The last part of the memory I want to discuss today is the Peripherals. It splits into 5 smaller chunks with Reserved memory in between them. Those chunks are: APB1, APB2, AHB1, AHB2, AHB3. Those parts of memory are described just below the memory map. You will find for example that GPIOA - responsible for the pins connected to the A port, are controlled by AHB2 bus (fancy name for a chunk of memory in this specific case). What do I mean by controlled? Imagine this AHB2 memory space is just a row of switches, where every switch represents a bit. By flipping those bits to either 1 or 0 you can control specific parameters of the peripherals. You need to change baud rate of a serial communication on USART1 port? From table 16 you know the configuration bits are in 0x4001 3800 - 0x4001 3BFF space.
There isn’t much more in the memory… Just a bunch of reserved space (what’s there I wonder… anything? nothing?). There is also this ARM fundament I was writing about - ARM Cortex-M4 with FPU Internal Peripherals… because as I have said:
Links worth checking out: